On high-performance parallel decimal fixed-point multiplier designs

On high-performance parallel decimal fixed-point multiplier designs

Radix - 10 Parallel Decimal Multiplier

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of p...

Analysis on FPGA Designs of Parallel High Performance Multipliers

For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. In this paper, optimized high performance parallel GF(2 233 ) multipliers for an FPGA realization were designed and the time and area complexities were analyzed. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. Fo...

Spherical Designs via Brouwer Fixed Point Theorem

For each N ≥ cdn 2d(d+1) d+2 we prove the existence of a spherical ndesign on Sd consisting of N points, where cd is a constant depending only on d.

Parallel Multiplier Designs for the Galois/Counter Mode of Operation

The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data integrity is achieved by chaining Galois field multiplication operations while a symmetric key block cipher such as the Advanced Encryption Standard (AES), is used to meet goals of...